module WRAP_SDP9K_9_36(
   CLKA,
   WEA,
   ADDRA,
   DINA,
   CLKB,
   ADDRB,
   DOUTB
   );


input                 CLKA;
input                 WEA;
input[9:0]            ADDRA;
input[8:0]            DINA;
input                 CLKB;
input[7:0]            ADDRB;
output[35:0]          DOUTB;

wire[0:0]             WEA_VECTOR;

assign  WEA_VECTOR[0]  =WEA;

XILINX_S6_SDP9K_9_36  INST_XILINX_S6_SDP9K_9_36(
   .clka              ( CLKA ),
   .wea               ( WEA_VECTOR[0:0] ),
   .addra             ( ADDRA[9:0] ),
   .dina              ( DINA[8:0] ),
   .clkb              ( CLKB ),
   .addrb             ( ADDRB[7:0] ),
   .doutb             ( DOUTB[35:0] ));

endmodule 


